Emerging transistor architectures
Ferroelectric MOSFETs, negative-capacitance devices, and the pursuit of favourable switching behaviour.
Microelectronics · IIT Jodhpur
Engineering
the invisible.
Exploring the devices and circuits that make tomorrow’s technology more capable, efficient, and beautifully small.
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Ideas at the scale of atoms
“Great technology often begins with a smaller question.”
A researcher's lens
From device physics to circuit behaviour, Ankush’s work explores how careful engineering at the transistor level can shape better electronic systems.01 / Research directions
Curiosity, in layers.
A connected view of emerging devices, compact circuit design, and the trade-offs that define low-power electronics.
Energy-aware VLSI systems
Examining power, delay, and operating conditions in memory and logic circuits for efficient design.
Device-to-circuit insight
Using simulation, benchmarking, and noise analysis to connect device choices with practical performance.
02 / Selected work
Ideas, made tangible.
A selection of conference contributions, technical reviews, and design projects across semiconductor devices and VLSI.
2025
Ferroelectric stacking in FET structures
Explored approaches to ferroelectric stacking, device behaviour, and benchmarking at the 20 nm technology node. Research paper accepted for presentation at VLSI SATA 2025.
2024
Ferroelectric MOSFET design and comparison
Designed a FeMOSFET using Synopsys EDA tools and compared modelling approaches in Synopsys and Silvaco; work accepted as a book chapter for ICICS.
2024
Negative capacitance in NC-TFETs
Reviewed negative-capacitance approaches for low-power TFET applications, including strengths, limitations, and critical device parameters.
Device modelling / Jan — Mar 2025
Noise analysis of vertical & U-shaped NC-TFETs
Design, flicker and shot-noise analysis, and benchmarking for low-power device structures.
Circuit design / Aug — Oct 2024
6T SRAM cell for power optimisation
Designed and analysed a 45 nm memory cell across operating voltages and frequencies using Cadence Virtuoso.
03 / The journey
Built on foundations.
A path through engineering, device modelling, and the questions that lead to deeper research.
CURRENT
PhD research in Microelectronics
Indian Institute of Technology Jodhpur
As shared in this portfolio brief
2023 — 2025
M.Tech, VLSI Design
Lovely Professional University, Punjab · CGPA 8.60
2019 — 2023
Bachelor of Education, Science
National Institute of Technology Puducherry · CGPA 7.25
2024 — 2025
Research presented & accepted
ICICS · Engineering Research Express · VLSI SATA
Ankush Mondal · Microelectronics researcher04 / About Ankush
Research with
purpose.
Ankush Mondal is a microelectronics researcher at IIT Jodhpur, interested in the fundamental devices and thoughtful circuit design that can move electronics toward lower power and greater capability. His work spans transistor modelling, VLSI design, simulation, and technical communication.
Synopsys EDASilvaco / InspectCadence VirtuosoVerilog HDLPythonDevice modelling
Discuss research or collaboration ↗05 / Get in touch
Good ideas
begin with hello.
For research conversations, collaboration, academic opportunities, or simply to connect, send a note directly to Ankush on WhatsApp.
+91 8900 927 463